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| R EM MICROELECTRONIC - MARIN SA H6061 3V Self Recovering Watchdog Description The H6061 is a combined initialiser, watchdog and voltage monitor. The circuit is a low voltage low power monolithic CMOS device combining a series of voltage comparators and a programmable timer on the same chip. The device is specially suited to telecommunications applications where 3 V working is expected, for functions such as supply voltage and microprocessor monitoring. The reset outputs are self recovering after a watchdog timeout, enabling the circuit to work with standalone systems without any external pushswitch or control signal to restart after a watchdog timeout. The circuit provides a reset signal of both polarities. The state of the outputs is defined down to 1.6 V. An internal debouncer ensures power-up performance for fast-rise supply lines. Features Watchdog fully operational from 2.7 to 5.25 V Regulated DC voltage monitor, internal voltage reference Self recovering watchdog function: reset goes active after the 1st timeout period, reset goes inactive again after the 2nd timeout period, repeated active reset signal until the system recovers Standard timeout period and power-on reset time (100 ms), externally programmable from 3 ms to 3 mins if required Works down to 1.6 V supply voltage Low voltage alarm prior to reset on power-down Reset outputs of both polarities Open drain outputs SO8 package Applications Microprocessor and microcontroller systems Point of sales equipment Telecom products Automotive subsystems Microcontroller 68HC05 applications Typical Operating Configuration 5V Pin Assignment H6061 VIN TCL VSS VDD RES SAVE RES NMI RES I/O P GND Fig. 1 Fig. 2 Copyright (c) 2004, EM Microelectronic-Marin SA 1 www.emmicroelectronic.com R H6061 Absolute Maximum Ratings Parameter Voltage VDD to VSS Voltage at any pin to VSS Voltage at any pin to VDD Voltage at VIN to VSS Current at any output Storage temperature Electrostatic discharge max. to MIL-STD-833C method 3014 Symbol VDD VMIN VMAX VINMAX IMAX TSTO VSmax Conditions - 0.3 to + 5.6 V - 0.3 + 0.3 + 12 V 10 mA -65C to +150C 1000V Table 1 Handling Procedures This device has built-in protection against high static voltages or electric fields; however, anti-static precautions must be taken as for any other CMOS component. Unless otherwise specified, proper operation can only occur when all terminal voltages are kept within the voltage range. Unused inputs must always be tied to a defined logic voltage level. Operating Conditions Parameter Operating temperature Industrial Supply voltage Version 11,12 RC-oscillator programming External capacitance External resistance * Leakage < 1A Table 2 Symbol Min. TAI VDD VIN C1 R1 -40 2.7 0 Max. Units +85 5.25 12 1 C V V F k Stresses above these listed maximum ratings may cause permanent damages to the device. Exposure beyond specified operating conditions may affect device reliability or cause malfunction. 10 Electrical Characteristics VDD = 5.0 V, TA = -40 to +85 C, unless otherwise specified Parameter VDD activation threshold VDD deactivation threshold Supply current Input VIN, TCL Leakage current TCL input low level TCL input high level Leakage on pins SAVE , RES , RES Symbol VON VOFF IDD IP VIL VIH IOLK IOL IOL IOL Test Conditions TA = 25 C TA = 25 C RC open, TCL at VDD or VSS VSS < VIP Typ. VON-0.3 80 Max. 2.7 140 Units V V A A V V A mA mA A Table 3 0.005 2.4 1 0.8 O/P drive logic low VOUT = VDD VOL = 0.4 V VDD = 3.5 V; VOL = 0.4 V VDD = 1.6 V; VOL = 0.4 V 4 2 80 0.050 8 1 VIN Surveillance Voltage thresholds at TA = 25 C Version No. 25 Thresholds VSH VSL VRL 1.54 1.50 1.46 at VDD 2.7 - 5.0 V Threshold Voltage Tolerance 10% Threshold Ratio* 2% Pin VIN Input 100 M Table 4 * Threshold ratio defined as VSH / VSL or VSL / VRL. Timing Characteristics VDD = 5.0 V, TA = -40 C to +85 C, unless otherwise specified Parameter Propagation delays TCL to output pins VIN to output pins Logic transition times on all output pins Timeout period TTCL input pulse width Power-on reset debounce Fastest pulse VIN with debounce Symbol Test Conditions TDIDO Min. Typ. 250 4 30 60 150 10 100 TTO/64 -40 to +85 C Max. 500 10 100 160 Units ns s ns ms ns ms s Table 5 TAIDO TTR TTCL TTO Excluding debounce time TDB Load 10 k, 100 pF RC open, unshielded, TA = 25 C TDB TVINL Copyright (c) 2004, EM Microelectronic-Marin SA 2 www.emmicroelectronic.com R H6061 Timing Waveforms Voltage Reaction: VDD Monitoring VDD VON VOFF VIN monitoring enabled Fig. 3 Voltage Reaction: VIN Monitoring VIN VSH VSL VRL Conditions: VDD > VON. No timeout. TTO 0 SAVE RES RES Timer Start Power-on Reset TVIN TTO TDB TDB Timer Stop Timer Start Power-on Reset No Power-on Reset (as VIN > VRL) Fig. 4 Timer Reaction TTCL TCL Conditions: VIN > VRL after power-up sequence TTO TTO TTO RES TTO RES Timer Reset Timeout Timer Reset Timer Reset Fig. 5 Copyright (c) 2004, EM Microelectronic-Marin SA 3 www.emmicroelectronic.com R H6061 Combined Voltage and Timer Reaction VIN VSH VSL VRL TDB SAVE RES RES TTO TTO TTO TCL Initialisation RES RES Timeout Recover Timer Reset Timer Stop Fig. 6 Block Diagram VIN Band-Gap Reference VSH + + Save Control SAVE VSL + VRL Reset Control RES RES + VSS RC OSC Timer TCL Fig. 7 Copyright (c) 2004, EM Microelectronic-Marin SA 4 www.emmicroelectronic.com R H6061 Pin Description Pin Name 1 2 3 4 5 6 7 8 VIN TCL RC VSS RES SAVE RES VDD Function Voltage monitoring input Timer clear input signal RC oscillator tuning input GND terminal Reset output, open drain Save output, open drain Positive reset output, open drain Positive supply voltage Table 6 Timer Programming A single timeout period TTO is used for the initialization reset duration and the watchdog timeout. With pin RC unconnected, the on-chip RC oscillator and divider chain give a timeout period TTO of typically 100 ms. A resistor to VDD will shorten this time, and a capacitor to VSS will lengthen it (see Fig. 11). An approximation for calculating trial values given in milliseconds by the formula: TTO = Functional Description Thresholds and Outputs The H6061 has open-drain outputs and voltage thresholds on pin VIN of typically 1.5 V. Internal Voltage Comparators The voltage comparators detect the voltage applied to pin VIN and compare it with thresholds VSH, VSL and VRL. The H6061 is designed for monitoring regulated DC voltages and has bandgap thresholds independent of VDD. The reaction of the H6061 to voltage changes on pin VIN is given in Fig. 4. During powering-up, the outputs are active. After VIN reaches the VSH level, pin SAVE deactivates after a short debounce time TDB to allow for fast ramp-ups. The initialization time TTO then passes before the two reset outputs go inactive. Thereafter, when the voltage on pin VIN falls below the VSL level, pin SAVE goes active low as a first warning. If VIN then drops below the VRL level, the reset signals go active and are guaranteed down to 1.6 V. The reset outputs react also to timeouts (see "Timer clearing"). Note that when the supply voltage VDD is below the level VOFF (about 2.2 V), all outputs are in the active state for any allowed voltage of VIN. Voltage Programming The H6061 was designed to give the best compromise in normal usage (see Table 3). Its voltage threshold can be programmed by an external resistor divider or a potentiometer to react at proportionally higher voltage levels (see Fig. 8 below). Voltage Programming 0.75 + (32 + C1) * 1.6 * 8.192 V - 0.8 4.8 + DD R1 R1 min. = 10 k, C1 max. = 1 F If R1 is in M and C1 in pF, TTO will be in ms. Choice of component values must be determined in practice. To have a square wave of period 2TTO, simply connect pin TCL to VDD or VSS and take the signal output from a reset pin. Timer Clearing A negative edge or pulse at the TCL input longer than 150 ns will clear the timer and deactivate the reset outputs under normal running conditions (see Fig. 3). TCL will however have no effect either when VDD < VOFF or during the initialization period before the deactivation of the reset pins. Combined Voltage and Timer Action In Fig. 6 is a typical sequence of power-up, watchdog run, and power-down. During initialization the SAVE pin deactivates one debounce delay time TDB after VIN rises above VSH, or when the power line VDD rises above VON, whichever happens last. The reset pins only deactivate one timeout period TTO afterwards to free the watchdog timer and end the initialization. Note that either VIN falling below VRL threshold or VDD below VON will cause an initialization upon recovery. Following initialization, the watchdog timer will time out after time TTO unless at least one TCL pulse clears it. On timeout the reset pins reactivate for a further TTO period before deactivating again for another try. A TCL pulse will deactivate any timeout reset, and another TCL pulse must follow within a time TTO to keep reset inactive. If no TCL pulses come at all, the reset pins go square-wave. Power-down overrides all this however. A falling voltage on VIN gives a warning SAVE = 0 signal at VIN = VSL before activating the reset pins as soon as VIN drops below VRL. The H6061 has fixed thresholds and low hysteresis for monitoring regulated DC lines. Additional protection is provided in case VDD supply falls over about 10% below VON which thereupon activates all outputs at once. Copyright (c) 2004, EM Microelectronic-Marin SA 5 www.emmicroelectronic.com R H6061 Typical Applications Microprocessor Watchdog with Voltage Monitor Selection of Watchdogs for Each Application The H6061 is designed for monitoring regulated DC voltages anywhere between 2.7 and 5.25 V. Typically, it is used to monitor VDD with pin VIN tied to the midpoint of a voltage divider (see Fig. 8). This arrangement has the advantage of being able to trigger at selectable voltage limits, i. e. it can be used where the regulated voltage is below 5 VDC. Industrial Heavy-Duty Utilisation The H6061 debounce protects against reactions due to fastrise power lines, but absolute maximum ratings must be respected. With its flexibility of voltage programming and supply voltage the H6061 can allow for voltage drops along supply lines, so it can be placed remotely, like on plug-in boards (see Fig. 9). The H6061 is suitable for supply voltages down to 2.7 VDC. As the H6061 is designed to be sensitive to voltage changes, fast switching lines, like address/data bus lines should not be run between the VDD and VSS supply lines near the H6061 without ground-plane shielding. Tracks from components to pin RC must be kept very short. Pin RC if left free should be shielded with a ground ring in noisy environments. The H6061 has only 40 mV hysteresis specially for monitoring regulated DC. Pin VIN must be protected from any significant mains ripple or RFI (see Fig. 10). It should be placed as near as possible to the point where voltage is to be monitored. Pin VIN is protected by an internal resistor (nominal 15 k) against voltages in excess of VDD. In some environments this may however pick up enough mains ripple or RFI to distort the voltage detection thresholds or even cause unwanted sporadic resets in the absence of adequate shielding or filtering on VIN. The H6061 has sufficient immunity to ripple and interference on the VDD supply line, but if it is important that a system meet severe criteria for injected spikes and RFI, then care must be taken also decouple VDD from these influences, as system protection must continue even under these conditions. With normal series voltage regulators, the regulated 5 VDC output voltage follows the DC rough voltage within 1.5 V on powering up. If the application has pin VIN monitoring the DC rough, the internal inputs to the on-chip comparators will not rise above VDD if the H6061 is correctly programmed. With switched-mode power supplies however, the DC-rough voltage on power-up rises almost to its working level before the 5 VDC line starts to ramp up. The H6061 has been specially designed to work under these extreme conditions but care must be taken not to exceed absolute maximum ratings. In addition to the voltage monitoring on pin VIN, a final protection is given by the H6061 monitoring its own VDD supply. If a system malfunction causes VDD to fall below VOFF even though pin VIN stays high, then all outputs go active at once. Copyright (c) 2004, EM Microelectronic-Marin SA 6 www.emmicroelectronic.com R H6061 Combined Supply Monitor, Initializer and Watchdog VIN shield or 2) depcoupling optional against interference 1) External Programming of RC Oscillator VDD TCL RC C1 VSS TO RES R1 TCL RC VSS VDD TO RES R1 TCL RC C1 VSS VDD TO RES C1 increases TTO R1 shortens TTO This circuit provides independent programming of both timeout period and power-on reset delay. Fig. 11 Copyright (c) 2004, EM Microelectronic-Marin SA 7 www.emmicroelectronic.com R H6061 Package Information Dimensions of 8-Pin SOIC Package D C E 0 - 8 L H Dimensions in mm Min Nom Max A 1.35 1.63 1.75 A1 0.10 0.15 0.25 B 0.33 0.41 0.51 C 0.19 0.20 0.25 D 4.80 4.93 5.00 E 3.80 3.94 4.00 e 1.27 H 5.80 5.99 6.20 L 0.40 0.64 1.27 Fig. 12 Fig. 12 A1 B A e 4 3 2 5 6 7 8 Ordering Information When ordering, please specify the complete Part Number Part Number H6061V25SO8A H6061V25SO8B Version Package Delivery Form Package Marking (first line) Temperature V25 8-pin SOIC 8-pin SOIC Stick Tape&Reel 606125 606125 -40C to +85C Note: other versions are no longer available EM Microelectronic-Marin SA cannot assume responsibility for use of any circuitry described other than circuitry entirely embodied in an EM Microelectronic-Marin SA product. EM Microelectronic-Marin SA reserves the right to change the circuitry and specifications without notice at any time. You are strongly urged to ensure that the information given has not been superseded by a more up-to-date version. (c) EM Microelectronic-Marin SA, 07/04, Rev. H Copyright (c) 2004, EM Microelectronic-Marin SA 8 www.emmicroelectronic.com |
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